(b) Larger cache capacities reduces miss rate but may incur longer hit time and higher cost and power.

(c) Greater associativity reduces conflict misses. Greater associativity can come at the cost of incrcased hit time.

(a) In a multilevel cache system, the first-level cache can be small enough to match a fast clock cycle time, yet the second-level (or third-level) cache can be large enough to capture many accesses that would go to main memory.

(b) Most proces ssors give cache write misses priority over read misses to reduce miss penalty.

(c) A common optimization is to use the page offset to index the cache in order to remove the translation lookaside buffer (TLB) access from the critical path.

(a) Performance can be improved by renaming register R1 in instruction [1], [2], and [3].

(b) Performance can be improved by renaming register R4 in instruction [5] and [6].

(c) Suppose the register-renamed version of the above code is resident in the RS in clock cycle N, with latencies LW = +4, SW = +1, ADDI=+0, SUB=+0, and BNZ=+2. The number of clock cycles taken by the code sequence is 14.

(a) Suppose that the RS is empty and the front end (decoder/register-renamer) will continue to supply two new instructions per clock cyclc. In cycle 0, the first two register-renamed instructions of this sequence appear in the RS. Assume it takes one clock cycle to dispatch any op in addition to the functional unit latencies. Then 9 clock cycles are required in the first iteration of this code sequence.

(b) Adding another ALU can save two clock cycles.

(c) Adding another LD/ST can save four clock cycles.

110年 - 110 國立臺灣大學_碩士班招生考試_電機工程研究所丙組:計算機結構與作業系統(A)#102089

109年 - 109國立臺灣大學_碩士班招生考試_電機工程研究所丙組:計算機結構與作業系統(A)#105855