(b) (10%)試計算缺席次數(解釋變數)與學期成績(被解釋變數)的回歸式。

8. (12%)試寫出樣本平均數() 及樣本比例() 的抽樣分配(sampling distribution)。 (請列出各抽樣分配的平均數、變異數及樣式(shape)) _________________________________________________________________________  附表：

(Problem 1] (20%) Terminology Explanation (a) Pipeline Processing (b) Superscalar Processor (c) RISC (d) GPGPU

(Problem 2] (20%) Suppose we are considering a change to an instruction set. The base machine is a load-store machine. Measurements of the load-store machine showing the instruction mix and clock cycle counts per instructions are given in the following table: Let's assume that 30% of the ALU operations directly use a loaded operand that is not used again. We propose adding ALU instructions that have one source operand in memory. These new register-memory instructions have a clock cycle count of 2. Suppose that the extended instruction set increases the clock cycle count for branches by 1, but it does not affect the clock cycle time. Would this change improve CPU performance? Explain your answer.

(Problem 3] (20%) A set associative cache has a block size of four 32-bit words and a set size of 4. The cache can accommodate a total of 256K words. The main memory size that is cacheable is 1024M * 32 bits. Design the cache structure and show how the processor's addresses are interpreted.

(1) Support add, sub, and sgt (set on great than) functions. Their operation selection bits (op_sel) are as follows: add(00), sub(10), sgt(11),

(2) Report the result status in sign, zero, overflow, and carry bits.

(a) (10%) Show the timing of this instruction sequence for the five-stage instruction pipeline with normal forwarding and bypassing hardware. Assume that branch is handled by predicting it has not taken. How many eycles does this loop take to execute?

(b) (10%) Assuming the five-stage instruction pipeline with a single-cycle delayed branch and normal forwarding and bypassing hardware, schedule the instructions in the loop including the branch-delay slot. You may reorder instructions and modify the individual instruction operands, but do not undertake other loop transformations that change the number of op- code of instructions in the loop. Show a pipeline timing diagram and compute the number of cycles needed to execute the entire loop.

二、資料庫之 ERDiagram轉换為Tabl(十五分) 將下列ER Diagram轉換成Relational  Schema 表示並標示出各Relation Schema 的 Primary Key

三、一資料庫中擁有1000篇文章而與某主題(topic1)相關的文獻有100篇,某檢索者由此資料庫檢索到40篇文章,與topic1相關的文章有20篇,請問此次 檢索的精確率(Precision)、召回率(Recall)分別為多少?(共計十分)

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